1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically concerns a semiconductor memory device which is subjected to a high-quality testing operation even when the number of the test pins of a test device is smaller than the number of address pins or data pins of the semiconductor memory device.
2. Description of the Background Art
Upon carrying out a test on a semiconductor memory device, a test device is connected to the semiconductor memory device and data wiite and data read operations are executed. Then, depending on whether or not the readout data is coincident with the write data, a judgment is made as to whether or not the semiconductor memory device is flawless.
In the data writing and data reading operations at the time of this test, address signals are also externally input to the semiconductor memory device in the same manner as a normal operation, and word lines and paired bit lines to be activated are selectively specified by the address signals. Then, the data writing and data reading operations are executed in and from memory cells connected to the activated word lines and paired bit lines.
Therefore, in the conventional semiconductor memory device, the test has been carried out with the number of address pins being coincident with the number of test pins of the test device.
However, the semiconductor memory device tends to have an increase in the number of pins as it comes to have a higher capacity. For example, following a semiconductor memory device having a total number of 48 pins including 20 address pins, a semiconductor memory device having a total number of 52 pins including 21 address pins has been developed. Therefore, the test device has only 20 test pins to be connected to the address pins of a semiconductor memory device, and even when this is connected to the newly developed semiconductor memory device with 21 address pins, it fails to input address signals to the semiconductor memory device, resulting in a failure in carrying out the test on the semiconductor memory device connected thereto.
Moreover, this problem alises not only in address pins, but also in data pins for executing data input and output.
Therefore, the objective of the present invention is to provide a semiconductor memory device which can be subjected to a high-quality testing operation even when the number of the test pins of a test device is smaller than the number of address pins or data pins of the semiconductor memory device.
A semiconductor memory device in accordance with the present invention is provided with: n (natural number) number of input/output terminals for inputting n number of address signals; a command terminal for inputting a fixing command to fix the address signals to a first or second logic; a plurality of memory cells; a plurality of bit lines placed in correspondence with the plurality of memory cells; a plurality of word lines placed in correspondence with the plurality of memory cells; an inner circuit receiving m number of address signals through m (m: a natural number satisfying nxe2x88x92 greater than 1) number of input/output terminals among n number of input/output terminals upon entering a test mode, and based upon the fixing command, generating nxe2x88x92m number of first logical signals in which each of nxe2x88x92m number of address signals is fixed to a first logic or n m number of second logical signals in which each of nxe2x88x92m number of address signals is fixed to a second logic so as to output n number of inner address signals including the m number of address signals and the nxe2x88x92m number of first or second logical signals; and a row/column decoder decoding the address signals so as to activate the plurality of bit lines or the plurality of word lines based upon the n number of inner address signals.
In the semiconductor memory device of the present invention, following a shift to a test mode, a fixing command is input thereto, and operation are input thereto. Then, the inner circuit generates a first logical signal to fix un-input address signals to the first logic or a second logical signal to fix them to the second logic, and outputs the resulting signal to the row/column decoder together with the input address signals. In other words, the inner circuit generates the first or second logical signal fixed to the first or second logic in place of each of the un-input address signals so that it virtually generates each of the un-input address signals, and outputs the resulting signal to the row/column decoder. Based upon the input address signals and the first or second logical signal, the row/column decoder decodes row addresses or column addresses for selecting word lines or bit lines through which data is input and output to and from a plurality of memory cells.
Therefore, in accordance with the present invention, even when address signals the number of which is smaller than that in the normal operation are input thereto, it is possible to carry out the test on all the memory cells. As a result, even when the input/output lines of the test device are fewer than the address pins of the semiconductor memory device, it is possible to carry out a data input/output test on all the memory cells.
More preferably, based upon the fixing command, the inner circuit of the semiconductor memory device generates nxe2x88x92m number of the first or second logical signals with respect to nxe2x88x92m number of high order address signals among n number of address signals.
Among the n number of address signals, m number of address signals that are low order address signals are input to the semiconductor memory device. Then, the inner circuit generates the first or second logical signals with respect to the nxe2x88x92m number of the un-input high order address signals, and outputs virtually the same number of address signals as that of the normal operation to the row/column decoder, thereby making it possible to carry out the test.
Therefore, in accordance with the present invention, even when the number of address pins increases as a semiconductor memory device comes to have a higher capacity, the semiconductor memory device can be subjected to a testing operation by using the same number of address pins subjected to a testing operation by using the same number of address pins as that of conventional address pins.
More preferably, the inner circuit of the semiconductor memory device includes an interface circuit generating nxe2x88x92m number of pairs of third and fourth logical signals, based upon the fixing command and nxe2x88x92m number of logical circuits receiving a pair of the third and fourth logical signals, generating the first logical signal when the third logical signal has the first logic and the fourth logical signal has the second logic, and generating the second logical signal when the third logical signal has the second logic and the fourth logical signal has the first logic.
Upon receipt of a fixing command, the interface circuit generates the third and fourth logical signals as paired logical signals. Then, the logical circuit generates the first or second logical signal when either of the third and fourth logical signal has the first logic. Therefore, in accordance with the present invention, by receiving the fixing command, it becomes possible to virtually generate address signals without being input.
More preferably, each of the nxe2x88x92m number of logical circuits in the inner circuit includes a pad for receiving any one of address signals among nxe2x88x92m number of address signals, and outputs, as it is, the one of the address signals when the third and fourth logical signals have the second logic and one of the address signals is input through the pad.
When the input/output lines of the test device increases resulting in an increase in the address signals input from the test device, the inner circuit outputs the address signals that can be newly input, as they are, without generating the first or second logical signal to fix the address signals to the first or second logic. Therefore, in accordance with the present invention, testing operations having the same quality can be carried out by using a plurality of test devices having input/output lines the numbers of which are different from each other.
Moreover, the semiconductor memory device in accordance with of the present invention is operated by a first word configuration or a second word configuration different from the first word configuration and, comprises of: an input/output terminal for receiving a fixing command, a circuit generating a first word configuration switching signal for switching the word configuration thereof to the first word configuration and a second word configuration switching signal for switching the word configuration based upon the fixing command thereof to the second word configuration; and an input/output circuit switching the word configuration to the first or second word configuration based upon the first or second word configuration switching signal, and inputting and outputting data to and from the plurality of memory cells.
In the semiconductor memory device in accordance with the present invention, upon receipt of a fixing command, the word configuration switching signal generation circuit generates a first word configuration switching signal for making a switchover to the first word configuration or a second word configuration switching signal for making a switchover to the second word configuration. In other words, the first and second word configuration switching signals for switching the word configurations are generated inside the semiconductor memory device without externally receiving a command for switching the word configurations. Then, based upon the first or second word configuration switching signal thus generated, the input/output circuits switches the word configurations, and inputs and outputs the resulting data in and from the plurality of memory cells.
Therefore, in accordance with the present invention, the word configuration of the semiconductor memory device can be switched without providing an input/output terminal required for a command for switching the word configurations. Moreover, by receiving a fixing command for providing a smaller word configuration to the semiconductor memory device in a test mode, it is possible to carry out the test by using input/output terminals the number of which is smaller than that of the normal operation.
More preferably, the word configuration switching signal generation circuit of the semiconductor memory device includes an interface circuit for generating the first and second logical signals based upon the fixing command, and a logical circuit generating the first word configuration switching signal when the first logical signal has the first logic and the second logical signal has the second logic, generating the second word configuration switching signal when the first logical signal has the second logic and the second logical signal has the first logic.
Upon receipt of the fixing command, the interface circuit generates the first and second logical signals. Then, the logical circuit generates the first or second word configuration switching signal when either of the first and second logical signals has the first logic.
Therefore, in accordance with the present invention, by receiving the fixing command, it is possible to generate the word configuration switching signal for switching the word configurations inside the semiconductor memory device. As a result, it is possible to make a switchover between the word configurations of the semiconductor memory device without providing an input/output terminal receiving a command for switching the word configurations.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.